Because of its highly reduced weight and physical dimension compared to magnetic memories such as hard disk or floppy disk memories, flash memory has a tremendous potential in the consumers electronics market. Flash memories are high-density nonvolatile semiconductor memories offering fast access times. Compared to other nonvolatile semiconductor memories such as conventional EPROMs or EEPROMs, flash memories are most suitable for applications wherein there are expected frequent write and read operations. With the rapid growth of digital cameras and the desire for light-weight notebook PCs, the demand for even higher density flash memories is ever increasing.
In a typical flash memory operation, the gate electrode comprises a control gate and one or more floating gates separated by a thin dielectric layer. When the control gate is charged, hot electrons will travel across the thin dielectric layer and cause the floating gate to be charged. After the power is turned off, the oxide layer surrounding the floating gate prevents the charge from dissipated. The control-gate-to-floating-gate coupling ratio, which is related to the areal overlap between control gate and the floating gate, affects the read/write speed of the flash memory.
U.S. Pat. No. 5,506,160, the content thereof is incorporated herein by reference, discloses a self-aligned trench isolation scheme for achieving 0.8 .mu.m isolation spacing between the MOS select transistors in an alternate metal virtual ground (AMG) EPROM array. The '160 also discloses a detailed process to implement an N.sup.- source for the EPROM cells and trench isolation between select transistors. The inventors claimed that using their process, both poly topography and bit line/word line capacitance can be significantly reduced. In addition, a new poly stack self-aligned etch (SAE) scheme is presented which allows better poly2 critical dimension control and eliminate poly1 bridging. As a result, word line to word line spacing of an AMG EPROM array can be scaled down to 0.6 .mu.m and below to achieve 64 Mbit EPROM array.
U.S. Pat. No. 5,409,854, the content thereof is incorporated herein by reference, discloses a floating gate of a virtual-ground flash EPROM cell, which is formed over a portion of a pair of vertically-adjacent field oxide regions, is self-aligned to the field oxide regions by utilizing a stacked etch process to define the widths of both the floating gate and the field oxide regions. The inventor claimed that, as a result, the pitch of the cells in the X-direction can be substantially reduced.
While the above inventions might have offered some advantages in the manufacturing of flash memories, neither of them addressed the issue of how to improve the coupling efficiency between the floating gate and the control gate. Increased coupling ratio can be very beneficial in reducing the required operation voltage of memory cell. Because of the increasing importance of flash memories in consumer goods, it is important that substantial research and development efforts be devoted in this area so as to further improve the performance and quality of flash memory cells, especially for low-voltage operations.